Question

How many translation steps are required in a paged virtual memory system when an address miss occurs in both the TLB and the primary page table in physical RAM?

Accepted Answer

In a paged virtual memory system, an address miss in both the Translation Lookaside Buffer and the primary page table triggers a page fault, requiring a total of three distinct translation or retrieval steps. First, the hardware or operating system must access the page table directory or secondary page tables to confirm the virtual address is not mapped in physical RAM. Second, the operating system executes a page fault handler to locate the requested data on the disk and allocate a free frame in physical RAM. Third, the operating system updates the primary page table and the Translation Lookaside Buffer to reflect the new mapping between the virtual address and the physical frame. A Translation Lookaside Buffer is a high-speed cache that stores recent virtual-to-physical address translations to avoid slow memory lookups. The primary page table is a data structure stored in physical RAM that maps virtual memory pages to physical memory frames. A page fault is an exception raised when a process attempts to access memory that is currently not mapped to a physical RAM frame. Once these three steps are complete, the CPU restarts the original memory access instruction, which will now result in a Translation Lookaside Buffer hit.

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How many translation steps are required in a paged virtual memory system when an address miss occurs in both the TLB and the primary page table in physical RAM?