Question

When implementing a MIPS pipeline, which specific data hazard occurs when an instruction attempts to read a register before a preceding instruction has finished writing to it in the WB stage?

Accepted Answer

The specific data hazard described is a read-after-write hazard, commonly referred to as a RAW hazard. This occurs because the MIPS pipeline executes instructions in stages, meaning a subsequent instruction might reach its ID, or instruction decode stage, to read a register value before the earlier instruction has reached its WB, or write-back stage, to update that register with its result. Because the register file is only updated during the final WB stage, the reading instruction receives stale, incorrect data instead of the result calculated by the preceding instruction. For example, if an add instruction calculates a result that is intended for a subsequent subtract instruction, the subtract instruction will attempt to read the register value during its decode phase. If the add instruction has not yet reached the write-back phase, the register still contains the old, outdated value. To solve this, processors use forwarding, also known as bypassing, which routes the calculated result directly from the pipeline registers to the functional units before the write-back stage occurs, or they use stalling, which forces the pipeline to wait until the required data is available.

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When implementing a MIPS pipeline, which specific data hazard occurs when an instruction attempts to read a register before a preceding instruction has finished writing to it in the WB stage?